Semiconductor device

ABSTRACT

Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished. 
     The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.

SPECIFICATION

1. Technological Field

The present invention relates to a semiconductor device, and inparticular, provides a highly functional semiconductor integratedcircuit device for the realization of neural network computers (neuroncomputers). Furthermore, the present invention provides a highlyfunctional semiconductor integrated circuit device for the realizationof multivalent analog memory.

2. Background of the Invention

The pace of development in semiconductor integrated circuit technologyhas been startling, so that, for example, using dynamic memory as anexample, memories from 4 megabits to 6 megabits are already inproduction, while ultra-high density memories having capacities of 64megabits or more are being realized at the level of research. In 64megabit memories, approximately 120 million MOS transistors areintegrated on a silicon chip measuring at most 1 cm². Such ultra LSItechnology is applied not merely to memory circuits, but also to logicalcircuits; a variety of highly functional integrated circuits have beendeveloped, beginning with CPUs of from 32 bits to 64 bits.

However, when such logical circuits are used to construct, for example,a computer employing a method in which digital signals, that is to say,signals having two values, "1" and "0", are used to conductcalculations, it is necessary to employ the Neumann method, in whichinstructions are executed one by one in accordance with a previouslydetermined program. When such a method is employed, extremely high speedcalculations are possible with respect to simple arithmeticalcalculations; however, an enormous amount of time is required for, forexample, the calculations of pattern recognition or image processing orthe like. Furthermore, such a method is highly disadvantageous for thetype of data processing at which human beings excel, such as, forexample, association, learning, and the like, and research is currentlybeing conducted into various software technologies; however, the currentstate of affairs is such that rapid results have not been obtained.Here, a separate branch of research has been conducted in order to solveall these problems; in this research, the functioning of animal brainsis being studied, and attempts are being made to develop computers whichare capable of conducting calculations and processing which imitatessuch functions, that is to say, to develop neural circuit computers(neuron computers).

This research began in the 1940's; however, the field has becomeextremely active in recent years. This is the case because, in concertwith the development of LSI technologies, it has become possible torealize such neuron computers in hardware.

However, there remain a number of problems with the realization of suchneuron computers on LSI chips using present semiconductor LSItechnology, and the goal of practical application has not yet beenreached.

A discussion of the technological problems involved in the realizationof such computers in terms of LSI follows.

The human brain has an extremely complex structure, and the functionsthereof are of an extremely high level; however, the basic compositionof the brain is extremely simple. That is to say, the brain comprisesnerve cells having a calculating function, termed neurons, and nervefibers, which transmit the results of such calculations to otherneurons, thus serving, so to speak, as wiring.

In FIG. 14, a simplified model of the composition of the fundamentalunits of the brain is shown. References 1401a, 1401b, and 1401c indicateneurons, while references 1402a, 1402b, and 1402c indicate nerve fibers.1403a, 1403b, and 1403c are termed synapse junctions; these apply, forexample, a weighting w_(a) to a signal transmitted from, for example,nerve fiber 1402a, and input this into neuron 1401a. Neuron 1401acalculates the linear sum of the signal strengths with are inputtedthereinto, and when the total value thereof is in excess of a thresholdvalue, the nerve cell becomes active, and outputs a signal to nervefiber 1402b. If the total value is less than or equal to the thresholdvalue, the neuron does not output a signal. The outputting of a signalby the neuron when this total value exceeds the threshold value isreferred to as the `firing` of the neuron.

In an actual brain, such calculations, transmission of signals,application of weighting, and the like are all conducted by means ofelectrochemical phenomena; the signals are transmitted and processed aselectrical signals. The process of learning in human beings can thus beunderstood as the process of the alteration of weighting in the synapsejunctions. That is to say, the weightings are progressively revised soas to obtain a correct output in response to a combination of a varietyof inputted signals, and the weightings finally settle at the optimumvalues. That is to say, human intelligence is engraved in the brain asweightings in synapses.

A large number of neurons are connected to one another via synapses andthus form one layer. It is known that in the human brain, there are 6layers, one on top of the other. The realization of this type ofstructure and function as an LSI system employing semiconductor devicesis the most important task in the realization of neuron computers.

FIG. 15(a) serves to explain the function of one nerve cell, that is tosay, one neuron; this was proposed as a mathematical model in 1943 byMcCullock and Pitts (Bull: Math. Biophys. Vol. 5, p.115(1943)).Currently, a great amount of research is being conducted into therealization of this model in semiconductor circuits and the constructionthereby of a neuron computer. V₁, V₂, V₃, . . . , V_(n) indicate anumber n of input signals which are defined in terms of, for example,voltage sizes; these correspond to the signals which are transmittedfrom other neurons. References W₁, W₂, W₃, . . . , W_(n) indicatecoefficients which express the strength of the junctions betweenneurons; in biological terms, these are what are termed synapsejunctions. The function of the neuron is to operate in such a mannerthat when a value Z comprising the linear sum of each input V_(i)multiplied by the appropriate weight W_(i) (i=1/n) is in excess of afixed threshold value V_(TH) *, a value of `1` is outputted, while whenthis value Z is smaller than the threshold value, a value of `0` isoutputted. This can be expressed in the following manner: ##EQU1##

FIG. 15(b) shows the relationship between Z and V_(out) ; when Z issufficiently larger than V_(TH) *, a value of 1 is outputted, while whenZ is sufficiently smaller than V_(TH) *, a value of 0 is outputted.

When an attempt is made to realize this type of neuron as a combinationof transistors, it is not merely the case that a large number oftransistors are required, but it is also necessary to conduct theaddition operation by converting each signal into an electrical currentvalue, so that a large number of electrical currents are caused to flow,and a very large amount of power is consumed. In such a state ofaffairs, large scale integration is impossible. This problem was solvedby the invention of the neuron MOSFET (abbreviated to νMOS) (inventors:Tadashi Shibata, Tadahiro Ohmi, Japanese Patent Application No. Hei1-141463).

This invention succeeded in realizing the main functions of theoperation of a neuron while employing only one transistor, and moreover,it was possible to conduct the addition operations of the voltagesignals in an unconverted state, so that almost no power was consumed,and the invention was thus epoch-making in that respect. FIG. 16indicates in simplified form an example of the cross sectional structureof this νMOS; 1601 indicates, for example, a P type silicon substrate,references 1602 and 1603 indicate a source and a drain formed by meansof N⁺ diffusion layers, reference 1604 indicates a gate insulating film(for example, SiO₂ or the like) which is provided on the channel region,reference 1606 indicates a floating gate which is electrically insulatedand is in a potentially floating state, reference 1607 indicates aninsulating film comprising, for example, SiO₂ or the like, and reference1608 (G₁, G₂, G₃, G₄) indicates input gates, which correspond to theinputs of the neuron.

FIG. 17 shows a further simplification of the above in order to explainthe operation of the νMOS. If the capacitive coupling coefficientbetween each input gate and the floating gate is represented by C_(G),and the capacitive coupling coefficient between the floating gate andthe silicon substrate is represented by C₀, then the potential Z of thefloating gate can be expressed as follows:

    Z=-w(V.sub.1 +V.sub.2 +V.sub.3 +V.sub.4)                   (4)

    w.tbd.C.sub.G /(C.sub.O +4C.sub.G)                         (5)

Here, V₁, V₂, V₃, and V₄ represent voltages which are inputted into,respectively, input gates G₁, G₂, G₃, and G₄, and the potential of thesilicon substrate is 0 V; in other words, it is grounded.

If the floating gate is viewed as a gate electrode, then this νMOS is astandard N channel MOS transistor, and if the threshold voltage as seenfrom the floating gate (the voltage at which an inversion layer isformed on the surface of the substrate) is represented by V_(TH) *, thenwhen Z>V_(TH) *, the νMOS enters an ON state, while when Z<V_(TH) *, thetransistor is in an OFF state. That is to say, if an inverter circuitsuch as that shown, for example, in FIG. 18 is built employing one suchνMOS 1609, then it is possible to realize the functions of one neuron ina simple manner. References 1610 and 1611 indicate resistors which servein the construction of the inverter, and reference 1612 indicates anNMOS transistor. FIG. 19 shows V_(out1) and V_(out2) as a function of Z;with respect to an input such that Z>V_(TH) *, V_(out2) outputs a highlevel voltage of V_(DD). That is to say, the state of the firing of theneuron is realized.

As shown in Formula (4), it is possible to realize the fundamentaloperation of the neuron, in which the inputs into the neuron are addedat the level of voltage and the neuron fires when the linear sum thereofis in excess of the threshold value, by means of only one νMOS. Voltagemode addition is conducted, so that the only current flowing in theinput portion is the charge and the discharge current of the capacitor,and the size thereof is very small. In the inverter, a direct current iscaused to flow when the neuron fires; however, this is because resistor1610 is employed as a load, and if a νMOS gate having a CMOS structurein accordance with the above described invention (Japanese PatentApplication No. Hei 1-141463) is employed, it is possible to eliminatethis direct current.

FIGS. 20 and 21 show examples of the CMOS structure. FIG. 20 shows thecross sectional structure of the CMOS neuron gate in a schematic manner;reference 2001 indicates a P type silicon substrate, reference 2002indicates an n type well, references 2003a and 2003b indicate,respectively, a N⁺ source and drain, references 2004a and 2004bindicate, respectively, a P⁺ type source and drain, reference 2005indicates a floating gate, and references 2006a-d indicate,respectively, input gate electrodes. References 2007 and 2008 indicateinsulating films comprising, for example, SiO₂, while reference 2009indicates a field oxide film. FIG. 21 indicates an example of thestructure of one neuron circuit; reference 2010 indicates the CMOSneuron gate of FIG. 20, represented symbolically, and portions thereofwhich are numbered correspond to the numbering in FIG. 20. Reference2011 indicates a CMOS inverter, while references 2012 and 2013 indicate,respectively, a NMOS transistor and PMOS transistor. Furthermore,reference 2014 indicates the output of the neuron.

It is possible to construct a neuron using a small number of elements inthe above manner, and moreover, since the power consumption is extremelysmall, the νMOS is an indispensable element for the realization of aneuron computer.

However, in order to realize the neuron computer, another importantelement aside from the neuron is necessary, that is to say, the synapse.FIG. 22 shows an example of the basic structure of a neuron circuitwhich also contains synapse junctions constructed using conventionaltechnology.

Reference 2201 indicates a neuron circuit such as that shown, forexample, in FIG. 18, and reference 2202 indicates wiring which transmitsoutput signals from other neurons. Reference 2203 indicates synapsejunction circuitry; this circuitry serves to impart a weighting to theinputted signal. This comprises a source follower circuit in which aload resistance (R+R_(x)) is connected to the source 2206 of the NMOStransistor 2204. Accordingly, when the output signal V_(S) of a neuronwhich has fired is applied to the gate electrode 2205 of the NMOStransistor, a voltage of V_(S) -V_(TH) arises in source 2206 (here,V_(TH) indicates the threshold of the NMOS transistor 2204).

For example, if a MOS transistor in which V_(TH) =0 is employed, thenthe potential of source 2206 is equal to V_(s), this voltage is dividedamong the two resistors R and R_(x), and forms the output voltage of thesynapse junction circuitry; this is transmitted to neuron 2201 by meansof wiring 2207. The output voltage thereof is V_(s) ·R_(x) /(R+R_(x)); aweighting comprising R_(x) /(R+R_(x)) is thus multiplied by the signalvoltage V_(s). It is possible to modify the weighting by means of thealteration of the value of R_(x).

FIG. 23 shows an example of a method for the realization of variableresistance. If a constant voltage V_(GG) is applied to the gate of oneMOS transistor 2301, then this transistor will function as a singleresistor. It is possible to modify the resistance value by means ofchanges in the value of V_(GG).

Furthermore, FIG. 23(b) shows an example of the circuitry forcontrolling the value of V_(GG) ; this comprises a 4 bit binary counter2302 and a D/A converter 2303. The junction strength of the synapse isexpressed as a 4 bit binary number; this is converted to an analogvoltage by means of D/A converter 2303 and outputted as the value ofV_(GG). In order to strengthen the synapse junction strength, acountdown is is effected in the value of the counter by means of acontrol signal, and the value of V_(GG) is thus reduced. On the otherhand, when the synapse junction is to be weakened, a count-up iseffected, and the value of V_(GG) thus increases.

The difficulties involved in the use of synapse junction circuitry suchas that shown in FIGS. 22 and 23 will be discussed below.

First, the first difficulty involves the voltage division by means ofresistors which generates the weighting in FIG. 22. When this method isemployed, the output voltage multiplied by the weighting is maintainedby means of continuously causing a current to flow to the resistors, sothat power is constantly consumed in an amount of V_(S) ² /(R+R_(x)).When this is the case, even if the power consumption is reduced by meansof the application of νMOS in the neuron 2201, the power consumption ofthe circuitry as a whole will not be sufficiently reduced. If a twolayer neural network, in which one layer comprises a number n ofneurons, is considered, then the number of synapse junctions reaches n²,and there are many more synapses then neurons. Accordingly, to theextent that synapse junction circuitry which requires that a currentcontinually be caused to flow is employed, the construction of a neuralnetwork of a scale suited to practical application causes excessivepower consumption, and it is thus in practice impossible to design sucha system. It is possible to reduce the power consumption by means ofsetting R+R_(x) to a sufficiently high value; however, in such a case,the time constant required for the charging and discharging of C_(out)is extremely large and the operating speed of the synapse circuit isworsened significantly.

The second problem is that the circuitry shown in FIG. 23(b) whichdetermines the weighting in question of the junctions requires a largenumber of elements, and can not be integrated on a large scale. In orderto construct a neural network having a learning function, it isnecessary that the strength of each synapse junction may beappropriately altered, and that the values altered in this manner may bestored. In FIG. 23(b), a 4 bit binary counter is employed for thispurpose; however, even for this, a minimum of 30 MOS transistors arerequired. Additionally, a large number of elements are required toconstruct the D/A converter. Furthermore, these circuits consume a largeamount of power per synapse junction, and this is also disadvantageousfrom the point of view of power consumption.

A method in which an EPROM or E² PROM non-volatile memory of a floatinggate type is employed has been proposed as a method for the reduction ofthe number of elements necessary for synapse construction. In suchdevices, the threshold value changes based on the amount of chargewithin the floating gate, so that it is possible to store weighting inan analog manner by means of the amount of charge. The weighting isstored in one transistor, so that each individual synapse circuit can bemade smaller in comparison with the circuitry shown in FIG. 23(b).However, in order to read this out as a weighting, and to multiply thisby the output of the previous stage neuron, it is of course the casethat correspondingly complex circuitry is required. For example, if adifferential amplifier circuit using two E² PROM memory cells isconstructed (D. Soo and R. Meyer, "A Four-Quadrant NMOS AnalogueMultiplier," IEEE J. Solid State Circuits, Vol. sc-17, No.6, December1982) the results of the multiplication by the weighting are read out aselectrical current signals. It is thus not merely the case that a largesimplification of the circuitry can not be achieved but also that thepower consumed in the process of multiplication by the weighting bymeans of a constantly flowing current is extremely large, so that suchstructures can not be used in the construction of a large scale neuralnetwork.

A further serious problem is shown in FIG. 24.

FIG. 24(a) shows the threshold voltage (V_(TH)) of a E² PROM cell havinga tunnel junction as a function of the number of pulses used for datawriting. The program voltage is 19.5 V, and the width of the pulse is 5msec. When a positive pulse is applied to the control electrode for theprogram, electrons are injected into the floating gate, and thethreshold value is shifted in a positive direction. In the oppositecase, if a negative pulse is applied, electrons are released from thefloating gate, and the threshold value is shifted in a negativedirection. As is clear from the Figures, the threshold value is greatlyshifted as a result of the initial pulse, and only extremely smallvariations are seen as a result of subsequent pulses. In this case, itis impossible to adjust the synapse weighting to a large number oflevels by fine alterations in the threshold value.

The reason for this can explained in the following manner.

FIG. 24(b) shows the state of the change over time in the number (n) ofelectrons injected into the floating gate when a positive programvoltage is applied in the form of a step function. It can be seen that alarge number of electrons are injected at the initial period of voltageapplication, and this number subsequently exhibits almost no increase.This forms the basis of charge injection. This is so because the currentflowing through the insulating film, termed Fowler-Nordheim tunneling,is dependent on a difference in potential V between the two ends of theinsulating film, in accordance with the following formula:

(Arithmetical Formula 2)

    I ∝V.sup.2 exp(-b/V)                                (6)

That is to say, when the number of electrons in the floating gateincreases as a result of the initial tunneling current, the potential ofthe floating gate decreases as a result of this, V becomes smaller, andas a result, the tunneling current decreases exponentially. In order toregulate the tunneling current at a constant value, and to preciselymodify the synapse weighting, it is necessary to precisely control thesize of the pulse voltage or the pulse width in accordance with theamount of the charge within the floating gate, and this results in aneed for further large amounts of circuitry.

In short, it must be said that the construction of a neural networkusing the conventionally known technology is essentially impossible fromthe point of view of a reduction in power consumption to a low level,large scale integration, and precision of synapse weighting.Accordingly, it is impossible to realize a neuron computer usingconventional technology.

The present invention was created in order to solve the problemsdescribed above; it provides a semiconductor device which is capable ofrealizing synapse junctions having an extremely small power consumptionand employing a small number of elements, and which is capable ofrealizing a neuron computer chip which is integrated on a large scale,allows highly precise synapse weighting, and which has a low level ofpower consumption.

DISCLOSURE OF THE INVENTION

The semiconductor device in accordance with the present invention isprovided with: a floating gate which is electrically insulated; a firstelectrode for charge injection, which is connected via a firstinsulating film with the floating gate; at least one second electrodefor programming pulse application, which is connected to the floatinggate via a second insulating film; and at least one MOS type transistorwhich uses the floating gate as the gate electrode thereof;characterized in that a mechanism for setting the potential of the firstelectrode to a predetermined value determined by the potential of thefloating gate, by means of a charge supplied from the source electrodeof the MOS transistor; and a mechanism for the transferring of chargesbetween the floating gate and the first electrode, via the firstinsulating film, by means of the application of predetermined voltagepulses to the second electrode, are provided.

The present semiconductor device makes possible the construction ofsynapse junctions using a small number of elements, and moreover, hasextremely small power consumption, so that the large scale integrationand reduction in power consumption to a low level of neural networksbecome possible. Furthermore, the highly precise modification of synapseweighting values becomes possible, and as a result of this, it ispossible to realize for the first time a neuron computer chip havingpractical application.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram which plains a first embodiment of thepresent invention.

FIG. 2 is a circuit diagram which explains the first embodiment of thepresent invention.

FIG. 3 is a circuit diagram which explains the first embodiment of thepresent invention.

FIG. 4 is a circuit diagram which explains the first embodiment of thepresent invention.

FIG. 5 shows the results of measurements conducted with respect to thecircuitry shown in FIG. 1.

FIGS. 6(a)-6(b) show actually measured data for the purposes ofcomparing the embodiment of the present invention with a conventionalexample.

FIG. 7 is a circuit diagram explaining the first embodiment of thepresent invention.

FIG. 8 is a circuit diagram explaining a second embodiment of thepresent invention.

FIG. 9 is a circuit diagram explaining a third embodiment of the presentinvention.

FIG. 10 is a circuit diagram explaining a fifth embodiment of thepresent invention.

FIG. 11 is a circuit diagram explaining a sixth embodiment of thepresent invention.

FIG. 12 is another circuit diagram explaining the sixth embodiment ofthe present invention.

FIG. 13 is a circuit diagram explaining a seventh embodiment of thepresent invention.

FIG. 14 shows a model of the fundamental unit of the brain.

In FIG. 15, FIG. 15(a) is a conceptual diagram explaining the functionof one nerve cell, that is to say, one neuron; FIG. 15(b) is a graphshowing the relationship between Z and V_(out).

FIG. 16 is a conceptual diagram showing a simplification of an exampleof νMOS structure.

FIG. 17 shows a further simplification of the structure of FIG. 16.

FIG. 18 is a circuit diagram of an inverter employing the neuron elementof FIG. 16.

FIG. 19 is a graph showing the relationship between the V_(out), V_(in),and Z in the circuit of FIG. 18.

FIG. 20 shows the cross sectional structure of a CMOS neuron gate.

FIG. 21 is a circuit diagram showing the structure of one neuroncircuit.

FIG. 22 is a circuit diagram showing an example of the fundamentalstructure of a neuron circuit containing synapse junctions which employνMOS transistors in accordance with the conventional technology.

In FIG. 23, FIG. 23(a) is a circuit diagram showing an example of amethod for the realization of variable resistance, while FIG. 23(b) is acircuit diagram showing an example of the control of the value ofV_(GG).

In FIG. 24, FIG. 24(a) is a graph showing the threshold voltage of anEPROM cell having tunneling junctions as a function of the number ofpulses used for data writing, while FIG. 24(b) is a graph showing thestate of the change over time in the number (n) of electrons injectedinto the floating gate during the application of a positive programvoltage in the form of a step function.

DESCRIPTION OF THE PREFERRED EMBODIMENT

(Embodiment 1)

A first embodiment of the present invention is shown in FIG. 1. In theFigure, V_(i) represents a control signal which can take the values of,for example, V_(DD), or 0.

Reference 101 indicates a floating gate; this forms the gate electrodeof NMOS transistor 102. Reference 103 indicates a PMOS transistor, andreferences 104 and 105 indicate NMOS transistors. The gates of PMOS 103and NMOS 104 are connected to the V_(i) signal line, while the gate ofNMOS 105 is connected to the V_(s) signal line. V_(p) indicates anelectrode for programming pulse application; this can also be used as aninput gate for determining the potential of floating gate 101.Furthermore, V_(E) also represents an electrode for programming pulseapplication. A SiO₂ film of a thickness of, for example, 100 Å, isformed between floating gate 101 and writing electrode 107; when thedifference in potential between these two is sufficiently large, forexample, when this difference reaches a level of 10_(V), a current flowsas a result of the Fowler-Nordheim tunneling phenomenon, and the amountof charge Q_(F) within floating gate 101 changes. If the potential ofthe floating gate is represented by Φ_(F) ^(S), then this is representedby the following formula:

    Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (6)

Here, C_(P) represents the capacity between V_(P) electrode 106 andfloating gate 101, C_(T) represents the capacity between V_(T) electrode107 and the floating gate, while C₀ represents the floating capacity.Furthermore, the capacity between V_(E) electrode 108 and electrode 107is represented by C_(E). Next, the operation of this circuitry will beexplained.

For the purposes of simplicity the threshold value of NMOS 105 is set to0 V, and furthermore, C_(T), C₀ <<C_(P), and C_(E) are established sothat C_(T) =C₀ =0, so that this may be ignored. At first, in the standbystate, that is to say, when V_(P) =V_(E) =0, and V_(i) =V_(s) =V_(DD),PMOS 103 is in an OFF state, and NMOS 104 and 105 are in an ON state,and the circuitry can be written equivalently to that in FIG. 2. Next,if V_(i) is set equal to 0, then PMOS 103 enters an ON state, and NMOS104 enters an OFF state, so that the circuit becomes equivalent to thatin FIG. 3. At this time, a current flows from power source V_(DD) intoV_(T) terminal 107 via NMOS transistors 102 and 105, so that thepotential thereof rises, and this rise in potential continues until NMOStransistor 102 enters an OFF state. Accordingly, the final value thereofis Φ_(F) ^(S) -V_(TN) *. Here, V_(TN) * represents the threshold valueas seen from the floating gate of NMOS 102. At this time, if Φ_(F) ^(S)-V_(TN) * is presumed to be within the range of the power sourcevoltage, then the difference in potential between electrode 107 andfloating gate 101 is not dependent on the amount of charge Q_(F) withinthe floating gate, and this is constantly at a level of V_(TN) * whenviewing the floating gate from electrode 107. After this, V_(S) is setequal to 0, and when NMOS 105 enters an OFF state, then the V_(T)terminal enters a floating state while maintaining a potential of Φ_(F)^(S) -V_(TN) *. This is shown in FIG. 4. In this state, when electronsare injected into the floating gate, if the program voltage is set toV_(PP) (V_(PP) represents a voltage equivalent to, for example, 10 V-V_(TN) *), and V_(P) is set equal to V_(PP), and if Φ_(F) ^(S)-V_(TN) * is within the range of the power source voltage, then thevoltage which is applied to tunnel oxide film portion 109 is notdependent on the amount of charge Q_(F) within the floating gate, butrather, a constant voltage of V_(PP) +V_(TN) * (that is, 10 V), whenviewing the floating gate from electrode 107, is applied, so that usingfixed pulse conditions, fixed tunneling is produced, and a fixed amountof electrons, independent of the amount of charge Q_(F) within thefloating gate, is injected into the floating gate. Furthermore, whenelectrons are removed from the floating gate, if the program voltage isset to V_(PP) ' (where V_(PP) ' is a voltage equivalent to 10 V+V_(TN)*), and V_(E) is set equal to V_(PP), then if Φ_(F) ^(S) -V_(TN) * iswithin the range of the power source voltage, the voltage which isapplied to the tunneling oxide film portion 109 is independent of theamount of charge Q_(F) within the floating gate, and a constant voltageof -V_(PP) '+V_(TN) * (that is to say, -10 V), when viewing the floatinggate from electrode 107, is applied, so that if fixed pulse conditionsare employed, a fixed tunneling is produced, and a fixed amount ofelectrons, independent of the amount of charge Q_(F) within the floatinggate, is removed from the floating gate. Furthermore, when removingelectrons from the floating gate, the same process can be conducted evenif V_(P) is set equal to -V_(PP). After injection or removal (afterapplication of the program voltage, or after the voltage of theelectrode applying the program voltage has been set to 0 V), V_(i)=V_(S) =V_(DD) (irrespective of the order of the switching) is set, andthe device is thus placed in the standby state.

By means of repeating this series of operations, under identicalconditions, a standardized amount of electrons is injected into orremoved from the floating gate at each single pulse. FIG. 5 shows theresults of a measurement with respect to the circuitry shown in FIG. 1and these results confirm this; the floating gate voltage Φ_(F) ^(S) inthe standby state of operations is plotted along the horizontal axis,while the amount of change ΔΦ_(F) ^(S) in the floating gate voltage wheninjection or removal of electrons is carried out by means of a singlepulse under identical conditions in the floating gate voltage is plottedon the vertical axis. In the circuit in which the measurement results ofFIG. 5 were obtained, a value of -2.5 V was used for V_(TN) *; however,insofar as Φ_(F) ^(S) -V_(TN) * is within the range of the power sourcevoltage, that is to say, so long as -2.5 V<Φ_(F) ^(S) <2.5 V, the amountof change Δ Φ_(F) ^(S) remains constant. The ΔΦ_(F) ^(S) of thecharacteristics of a conventional E² PROM decreases exponentially withrespect to the floating gate voltage, and this is plotted for referenceproposes. The black arrows in the Figure indicate the direction ofchange in accordance with the carrying out of injection or removal ofelectrons. When Φ_(F) ^(S) has other values, that is to say, when Φ_(F)^(S) -V_(TN) * is outside the range of the power source voltage, thenthe characteristics of a conventional E² PROM appear, and the constantvalue is lost; however, this presents no problem. The reason for this isthat it is possible to prevent a breakdown in insulation of the oxidefilm which is produced by the excessive injection of charge into thefloating gate or the excessive removal of charge therefrom. Furthermore,with respect to the synapses of the neural network, when hardwarelearning is conducted, the values of the synapse weighting, that is tosay, the amount of charge within the floating gate, reaches a maximum ora minimum, these values automatically become incapable of furtheralteration, and this is a highly desirable result in a hardware learningalgorithm.

In the measurement results shown in FIG. 5, a value of -2.5 V was usedas V_(TN) *; however, at other threshold values, the region within whichΔΦ_(F) ^(S) remains constant is merely shifted, so that identicalresults can be obtained. Additionally, FIG. 6 shows actually measureddata comparing both a conventional example and the present embodiment.In FIG. 6, after conducting one continuous injection operation, thethreshold value V_(TH) of the NMOS 102 as seen from terminal 106 wasmeasured. The amount of change ΔV_(TH) in the threshold value and theamount of change ΔΦ_(F) ^(S) in the floating gate voltage wereidentical, and using C as a constant, the relationship is one in whichV_(TH) =Φ_(F) ^(S) +C.

Here, at non-programming intervals, V_(P) =V_(E) =0 was established;however, V_(P) and V_(E) may represent other voltages. Additionally,with respect to C_(T), C₀ <<C_(P), and C_(E), C_(T) =C₀ =0, so that thiscould ignored; however, this was done in order to simplify theexplanation, and it is of course the case that other values may beemployed. Furthermore, the threshold value of NMOS 105 was set to 0 V;however, this may be set to other values. For example, if the thresholdvalue of NMOS 105 is set to V_(TN), then when V_(TN) >0, the maximumpotential of electrode 107 only rises to V_(S) -V_(TN). However, forexample, V_(S) may be set to a value of V_(DD) or more using a bootstrapcircuit or the like. Alternatively, in place of NMOS 105, the so-calledCMOS switch shown in FIG. 7 may be employed. In FIG. 7, reference 701indicates an NMOS transistor, reference 702 indicates a PMOS transistor,and reference 703 indicates a standard inverter.

The highly precise control of the amount of charge within the floatinggate using single pulses under identical conditions, which wasconventionally impossible when using floating gate type E² PROM nonvolatile memory without an external control circuit, as a result of thedependence of the Fowler-Nordheim tunneling current on the difference ofpotential between the ends of the insulating film, has become possibleby means of the present invention without the use of an external controlcircuit, and moreover, by means of simple circuitry. As a result,although in conventional neural networks the amounts of charge within E²PROM floating gates was monitored and precisely controlled one by one bymeans of a large scale computer, so that a very large amount of time wasrequired, by means of the present invention, this is completed afteronly one programming pulse, and the learning time is greatly shortened.

(Embodiment 2)

FIG. 8 is a circuit diagram explaining a second embodiment of thepresent invention.

The points of difference from FIG. 1 are that the floating gate 101 inFIG. 1 is divided into a region having an NMOS transistor and regionhaving V_(P) and V_(T), where these two regions are connected via aswitching transistor 805, and that NMOS transistor 105 is omitted.

In the Figure, V_(i) represents a control signal; it has the values of,for example, V_(DD) or 0. References 801 and 801' indicate floatinggates which are divided by switching transistor 805. 801' forms the gateelectrode of NMOS transistor 802. Reference 803 indicates a PMOStransistor, while reference 804 indicates an NMOS transistor. The gatesof PMOS transistor 803 and NMOS transistor 804 are connected to theV_(i) signal line, while the gate of switching transistor 805 isconnected to the V_(S) line. Reference V_(P) indicates an electrode forprogramming pulse application; this can also be used as an input gatefor determining the potential of floating gate 801. Furthermore,reference V_(E) also represents an electrode used for programming pulseapplication. A SiO₂ film having a thickness, for example, of 100 Å, isformed between floating gate 801 and writing electrode 807, and when thedifference in potential in these becomes sufficiently large, forexample, reaching a level of 10 V, then a current is caused to flow as aresult of the Fowler-Nordheim tunneling phenomenon, and the amount ofcharge Q_(F) within the floating gate changes. Here, if the potential ofthe floating gate is represented by Φ_(F) ^(S), then this is describedby the following formula:

    Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (7)

Here, C_(P) represents the capacity between V_(P) electrode 806 andfloating gate 801, C_(T) represents the capacity between V_(T) electrode807 and the floating gate 801, and C₀ represents the floating capacity.Furthermore, the capacity between V_(E) electrode 808 and electrode 807is represented by C_(E).

With respect to the operation, the NMOS 105 of Embodiment 1 iseliminated, and in its place, a switching transistor 805 is added, andthe changes in potential of all electrodes V_(i), V_(P), V_(E), V_(S),and V_(T) are unaffected thereby.

The basic principle thereof is that, because if the switching transistoris placed in an OFF state, the floating gate is divided into the twoportions 801 and 801', the potential of 801' of NMOS 802 remainsconstant even if programming pulses are applied to V_(P) or V_(E) duringthe injection or removal of electrons. By means of this, the value Φ_(F)^(S) -V_(TN) * read out from electron 807 can be maintained at aconstant level even while programming pulses are being applied to V_(P)or V_(E). Accordingly, effects identical to those of the firstembodiment can be obtained.

(Embodiment 3)

FIG. 9 shows a third embodiment of the present invention.

The differences between this embodiment and that shown in FIG. 1 arethat the PMOS transistor 103 in FIG. 1 is replaced by an NMOS transistor904, the gate electrode of this NMOS transistor 904 is connected to theV_(S) signal line, and the NMOS transistor 105 is eliminated.

Reference 901 indicates a floating gate; this functions as the gateelectrode of NMOS transistor 902. Reference 903 indicates an NMOStransistor. The gate of NMOS 903 is connected to the V_(i) signal line.V_(P) represents an electrode for the application of programming pulses;it may also be employed as an input gate for determining the potentialof floating gate 901. Furthermore, V_(E) also represents an electrodewhich is employed for the application of programming pulses. A SiO₂ filmhaving a thickness of, for example, 100 Å is formed between floatinggate 901 and writing electrode 906, and when the difference in potentialbetween these two is sufficiently large, for example, when thisdifference reaches approximately 10 V, then a current flows as a resultof the Fowler-Nordheim tunnelling phenomenon, and the amount of chargeQ_(F) within floating gate 901 changes. Here, if the potential of thefloating gate is represented by Φ_(F) ^(S), then this is described bythe following formula:

    Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (8)

Here, C_(P) represents the capacity between the V_(P) electrode 905 andthe floating gate 901, C_(T) represents the capacity between the V_(T)electrode 906 in the floating gate, while C₀ represents the floatingcapacity. Furthermore, the capacity between V_(E) electrode 907 andelectrode 906 is represented by C_(E).

With respect to operations, the PMOS 103 and NMOS 105 of Embodiment 1were eliminated, and in their place, a NMOS transistor 904 was added,and thereby, the changes in potential of all of the electrodes V_(i),V_(P), V_(E), V_(S), and V_(T) remain unaffected.

The basic principle thereof is that, if the NMOS transistor 904 is in anOFF state, the drain terminal of the NMOS transistor 902 is cut off fromthe power source, so that the potential of the source terminal NMOSterminal 902, that is to say, of V_(T) electrode 906, remains constanteven if programming pulses are applied to V_(P) or V_(E) during theinjection or removal of electrons. By means of this, the value Φ_(F)^(S) -V_(TN) * which was read out of electrode 906 remains constant evenwhile programming pulses are being applied to V_(P) or V_(E).Accordingly, effects can be obtained which are identical to those of thefirst embodiment.

(Embodiment 4)

In Embodiments 1 through 3 described above, an NMOS transistor having afloating gate was replaced by a PMOS transistor, and the polarity of atransistor having a gate connected to the V_(i) signal line wasreversed, that is to say, an NMOS transistor was replaced by an PMOStransistor, and a PMOS transistor was replaced by an NMOS transistor,and furthermore, the polarity of the two power supply lines wasreversed, and the signal line V_(i) was made an inverted V_(i), and evenwhen these things were carried out, effects could be obtained which wereidentical to those of Embodiment 1 by means of operations which wereidentical to those of Embodiment 1.

(Arithmetical Formula 3)

    inverted V.sub.i . . . V.sub.i  (identical hereinbelow)

(Embodiment 5)

FIG. 10 is a circuit diagram showing a fifth embodiment of the presentinvention.

The differences between this embodiment and that shown in FIG. 1 arethat the NMOS transistor 102 in FIG. 1 is replaced by a PMOS transistor1002, the V_(T) electrode 107 in FIG. 1 is connected not to the sourceterminal of the NMOS transistor 102 in FIG. 1, but rather to the sourceterminal of the PMOS transistor 1002, and the NMOS transistor 105 inFIG. 1 is eliminated.

In FIG. 10, reference 1001 indicates a floating gate; this functions asthe gate electrode of PMOS transistor 1002. Reference 1003 indicates aPMOS transistor, while reference 1004 indicates a NMOS transistor. Thegates of PMOS 1003 and NMOS 1004 are connected to the V_(i) signal line.V_(P) represents an electrode for programming pulse application; thismay also function as an input gate for determining the potential offloating gate 1001. Furthermore, V_(E) also represents an electrode forprogramming pulse application. A SiO₂ film having a thickness of, forexample, 100 Å, is formed between floating gate 1001 and writingelectrode 1006, and when the difference in potential between these issufficiently large, for example, when this difference reaches a level of10 V, a current is caused to flow as a result of the Fowler-Nordheimtunneling phenomenon, and the amount of charge Q_(F) within floatinggate 1001 changes. Here, if the potential of the floating gate isrepresented by Φ_(F) ^(S), then this is described by the followingformula:

    Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (9)

Here, C_(P) represents the capacity between V_(P) electrode 1005 andfloating gate 1001, C_(T) represents the capacity between V_(T)electrode 1006 and the floating gate, and C₀ represents the floatingcapacity. Furthermore, the capacity between V_(E) electrode 1007 andelectrode 1006 is represented by C_(E).

With respect to the operation, the NMOS 105 of Embodiment 1 iseliminated, and the V_(S) signal line is also eliminated, and as aresult, the changes in potential of V_(i), V_(P), and V_(E) remainunchanged. A point which should be noted is that the gates of PMOS 1003and NMOS 1004 are connected not to the signal line of V_(i) but to thesignal line of the inverted V_(i). By means of this, the potential V_(T)of electrode 1006 is such that when V_(i) =V_(DD), that is to say, whenthe inverted V_(i) =0, V_(T) =V_(DD) ; however, when V_(i) =0, V_(DD),that is to say, when the inverted V_(i) =V_(DD), then the potentialV_(T) of electrode 1006 has a value of Φ_(F) ^(S) -V_(TP) *, as inEmbodiment 1. Here, V_(TP) * represents the threshold value of PMOStransistor 1002 as seen from the floating gate. In this state, apositive program voltage is applied to V_(P) or V_(E).

The basic operating principle is that, using the fact that when apositive voltage is applied to the floating gate of the PMOS transistor1002, the PMOS transistor 1002 enters an ON state, after V_(i) hasbecome equal to 0, that is to say, the inverted V_(i) has become equalto V_(DD), the potential of the source terminal of PMOS 1002, that is tosay, the potential of V_(T) electrode 1006, remains constant even ifpositive programming pulses are applied to V_(P) or V_(E) duringinjection or removal of electrons. By means of this, the value Φ_(F)^(S) -V_(TP) * read out of electrode 1006 can be maintained at aconstant value even during the application of programming pulses toV_(P) or V_(E). Accordingly, effects identical to those of the firstembodiment can be obtained.

(Embodiment 6)

FIG. 11 is a circuit diagram explaining a sixth embodiment of thepresent invention. As shown in this diagram, the present invention maybe employed in a differential manner. In FIG. 11, reference 1101indicates a floating gate, which serves as the gate electrode of NMOStransistor 1102 and PMOS transistor 1103. V⁺ and V⁻ represent outputvoltages which appear in the terminals 1104 and 1104', respectively, ofthis circuit; these are coupled with electrode 1105 via capacitors C₁and C₂. Reference 1106 indicates an NMOS transistor, the gate electrodeof which is connected to signal line V_(S). If NMOS 1106 enters an ONstate when V_(S) =V_(DD), the potential of the floating gate 1101 isrepresented by Φ_(F) ^(S), and the threshold values of NMOS transistor1102 and PMOS transistor 1103 are represented by V_(TN) * and V_(TP) *,respectively, then when V_(i) =V_(DD), V⁺ becomes equal to 0 and V⁻becomes equal to V_(DD), and for example, if C₁ =C₂, and electrode 1105is placed in a floating state, then the potential V_(E) of electrode1105 becomes V_(DD) /2, and when V_(i) =0, V⁺ becomes equal to Φ_(F)^(S) -V_(TN) *, and V⁻ becomes equal to Φ_(F) ^(S) -V_(TP) *, thepotential V_(E) of electrode 1105 becomes equal to (2Φ_(F) ^(S)-V_(TN) * -V_(TP) *) /2, and a value is read out which is the voltage ofthe floating gate shifted by a constant. If |V_(TN) *|=|V_(TP) *|, thenV_(E) =Φ_(F) ^(S), and the voltage of the floating gate is read out inan unchanged fashion to electrode 1105.

When injection or removal of electrons is conducted, an appropriatevoltage is applied as V_(E), and effects identical to those ofEmbodiment 1 can be obtained by means of operations identical to thoseof Embodiment 1.

Furthermore, it is of course the case that the portion marked 1107 maybe exchanged for that in Embodiments 2-4. Furthermore, identical effectscan be obtained with the circuitry shown in FIG. 12.

(Embodiment 7)

FIG. 13 is a circuit diagram showing a seventh embodiment of the presentinvention.

In this embodiment, the electrode 108 in FIG. 1 of Embodiment 1 is madethe gate electrode of a CMOSνMOS inverter of a neuron circuit 1302, andthis is coupled with signal line V_(E) via switching transistor 1304.

The case is shown in which, in this circuit, reference 1301 is employedas a synapse of a neural network.

When electrons are injected or removed, the switching transistor 1304 isplaced in an ON state, an appropriate voltage supplied as V_(E), andthus effects identical to those of Embodiment 1 can be obtained by meansof operations identical to those in Embodiment 1.

When the potential of the floating gate 1306 is read out, the switchingtransistor 1304 is placed in an OFF state, electrode 1307 is placed in afloating state, and when V_(i) is set equal to 0 or V_(DD), the outputof the neuron circuit 1302 is determined by means of the value read outby means of capacitive coupling with electrode 1307.

In electrode 1307, a switching transistor which divides 1301 and 1302may be provided.

Furthermore, 1301 may be operated in a differential manner as inEmbodiment 6.

In Embodiments 1-7 described above, a plurality of electrodes for theapplication of programming pulses may be provided. By means of providinga plurality of such electrodes, programming may be conductedselectively. Additionally, it is of course the case that superioreffects may be obtained if a plurality of Embodiments 1-7 areappropriately combined.

INDUSTRIAL APPLICABILITY

By means of the present invention, it is possible to construct a synapsejunction using a small number of elements, and moreover, the powerconsumption thereof is extremely small, so that the large scaleintegration and reduction in power consumption of neural networksbecomes possible. Additionally, the highly precise modification ofsynapse weighting becomes possible, and by means of this, it becomespossible for the first time to realize a neuron computer chip on apractically applicable level.

We claim:
 1. A semiconductor device comprising:a first MOS transistorincluding an electrically isolated floating gate electrode, said firstMOS transistor further including a source electrode; a first electrodefor injecting a charge, said first electrode connected to said floatinggate by means of a first insulating film; a second electrode forapplication of a programing pulse to said device, said second electrodeconnected to said floating gate by means of a second insulating film; athird electrode for application of an programming pulse to said device,said third electrode connected to said first electrode by means of athird insulating film; and a second MOS transistor interconnecting saidsource electrode to said first electrode, whereby, after said second MOStransistor is placed in an on-state and the potential of said firstelectrode is set to a value which is determined by the potential of saidfloating gate by means of a charge supplied from said source electrode,said second MOS transistor is thereafter placed in an off-state, and apredetermined voltage pulse is applied to one of said second and thirdelectrode charge transfer is caused between said floating gate and saidfirst electrode.